Field tests of integrated circuits are becoming important for three main reasons. First, electronic components are increasingly used in safety critical systems such as automotive and medical electronics. Periodic testing of such safety critical systems is recommended through the lifetime of the device. Second, the user may need to check the operating parameters of the device during its use for conformance to specifications. This conformance may be improper due to design variability in deep sub-micron technologies. In addition various runtime environmental factors may change this conformance. Third, it is increasingly difficult to test for all defect models at time-zero manufacturing tests. Thus systems need to be monitored during their normal operation. These additional requirements are driven by the need for high dependability and low down-time in safety critical systems.
FIG. 1 illustrates an example of a built in self test (BIST) Architecture 100 known as a DBIST from Synopsys. In the Synopsys DBIST architecture, a linear feedback shift register (LFSR) based pseudo-random pattern generator (PRPG) 101 is initialized to a particular value or seed. The PRPG generates a new unique pattern each cycle of clock BIST_clk. The patterns generated are repeatable but appear random. This block functions as a pseudo-random pattern generator (PRPG). The patterns from the PRPG LFSR pass through a phase shifter 102. Phase shifter 102 is a block of combinational logic that converts the one-dimensional stream of pseudo-random patterns from PRPG 101 into a two dimensional array of values to load parallel scan chains of the circuit under test (CUT) 103.
As known in the art, such serial scan chains permit testing of the circuit under test as follows. Data is loaded into the registers of the circuit under test via the serial scan chains in a test mode. In the test mode each scan chain provides a serial path between an input, some of the data registers of the circuit under test and an output. Such an arrangement permits setting the conditions of the circuit under test into a desired state by scanning in the appropriate data. The set of parallel scan chains are generally designed to include registers storing data relevant to the internal condition of the circuit under test. After loading the data in this manner, the circuit under test operates in a normal mode responsive to its own clock signal (Core_Clk) for an interval. Following this operational interval the internal state of the circuit under test is output via the same scan chains. This view of the internal state of the circuit under test can be compared with an expected internal state.
In this prior art there are generally many scan chains. These scan chains are kept short to increase the controllability and observability of the design, reducing the pattern count. CUT 103 is run for an interval under clock Core_Clk. The scan chains capture data. Captured data is unloaded through scan chain outputs into a compactor 104 that compacts the test outputs. After 32 captures (known as one interval) in multiple-input signature register (MISR) 105, the state of the signature analyzer output via MISR_Scan_out is compared to the known signature of the fault free design. Any mismatch indicates that at least one erroneous value was unloaded from the scan chains. Multiple-input signature register (MISR) 105 is a modified LFSR. Compactor 104 is made of combinational logic. The signature analyzer is used to reduce the number of scan chain outputs allowing MISR 105 to be smaller. The test logic runs under control of BIST CTRL 106.
Traditional random pattern logic BIST with a single seed can result in only a finite set of care bits independent of circuit under test size. This limited set of care bits results in relatively low test coverage. DBIST such as illustrated in FIG. 1 addresses this problem by adopting periodic re-seeding technique. The initial and subsequent seeds are loaded from tester 110 to shadow register 107 via a shadow register scan in line. This seed is then transferred from shadow register 107 to PRPG 101 to start the test process. Thus in DBIST the seeds needed for the PRPG to generate test patterns are generated with deterministic automated test pattern generation (ATPG) techniques and loaded through tester channels.
The basic BIST architecture of FIG. 1 can be extended to support field self-test by providing enhancements like re-seeding through the device internal interface to the BIST controller, user programmable pattern counter for each seed, internal signature storage and comparison. FIG. 2 shows such modifications to the DBIST architecture illustrated in FIG. 1. Modified DBIST Architecture 200 illustrated in FIG. 2 is similar to FIG. 1. Like parts include like reference numerals. Under control of central processing unit (CPU) 210 self-test controller 211 controls use of external/internal memory 212. Self-test controller 211 periodically loads a new seed from external/internal memory 212 into shadow register 107 via shadow register scan-in to begin a new series of tests.
When logic BIST is employed for field-test, the seeds generally are stored on-chip. During self-test these seeds are periodically loaded into the LFSR to generate the patterns. To attain a desirable level of coverage may require a large number of seeds. This would require a large on-chip memory. Field tests using these traditional logic BIST techniques thus generally suffer from either low coverage or large overhead from the required on-chip memory for seed storage. An alternate to providing a large internal memory has the seeds transferred to the device from an external memory. This requires either no field test or a system level interface between the CUT and external memory requiring additional hardware and software support.